FSFD=0, IGNSF=0, CCIE=0, ERSAREQ=0, FDFD=0
Flash Configuration Register
| FSFD | Force Single Bit Fault Detect 0 (0): Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected 1 (1): Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 1.3.2.7) and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set |
| FDFD | Force Double Bit Fault Detect 0 (0): Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected 1 (1): Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as the FERCNFG[DFDIE] is set |
| RESERVED | no description available |
| IGNSF | Ignore Single Bit Fault 0 (0): All single bit faults detected during array reads are reported 1 (1): Single bit faults detected during array reads are not reported and the single bit fault interrupt is not generated |
| ERSAREQ | Erase All Request 0 (0): No request or request complete 1 (1): Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. |
| RESERVED | no description available |
| CCIE | Command Complete Interrupt Enable 0 (0): Command complete interrupt disabled 1 (1): Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. |